Arithmetic unit

ABSTRACT

The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.

This is a continuation application of U.S. patent application Ser. No.09/445,059, filed Dec. 2, 1999.

TECHNICAL FIELD

The present invention relates to an arithmetic unit and, moreparticularly, to an arithmetic unit which is used as a signal processor.

BACKGROUND ART

At present, image coding methods such as MPEG1, MPEG2, MPEG4, H. 261,and H.263 are standardized as the International Standards.

FIG. 14 is a block diagram illustrating a structure of an imageprocessing system based on these standards.

In the figure, reference numeral 1 denotes an encoder and numeral 9denotes a decoder. The encoder 1 comprises an input circuit 2, adiscrete cosine transform circuit 3, a quantization circuit 4, avariable-length coding circuit 5, and a bitstream transmitting circuit6. The decoder 9 comprises a bitstream receiving circuit 10, avariable-length decoding circuit 11, an inverse quantization circuit 12,an inverse discrete cosine transform circuit 13, and an output circuit14.

In the image processing system constructed as above, in the encoder 1,an image data is initially input from the input circuit 2, the inputimage data is cosine-transformed by the discrete cosine transformcircuit 3, then quantized, and variable-length coded by thevariable-length coding circuit 5, to obtain a code of various codelength. Then, this code and a code length 7 are output to the bitstreamtransmitting circuit 6. In the bitstream transmitting circuit 6, thecode is subjected to multiplexing using the code length 7 to obtain abitstream 8 and the bitstream 8 is output to the decoder 9.

In the decoder 9, this output bitstream 8 is received by the bitstreamreceiving circuit 10, and variable-length decoded and demultiplexedusing a code length 16 to obtain an original code 15, by a cooperativeoperation of the bitstream receiving circuit 10 and the variable-lengthdecoding circuit. This decoded and demultiplexed code 15 isinverse-quantized by the inverse quantization circuit 12 andinverse-discrete-cosine-transformed by the inverse discrete cosinetransformation circuit 13 to reproduce an original image data, and theoriginal image data is output from the output circuit 14 to outside.

The multiplexing processing in the bitstream transmitting circuit 6 andthe demultiplexing processing in the bitstream receiving circuit 10 areperformed by special use arithmetic units or performed by software.

FIGS. 9(a) to 9(c) are diagrams schematically illustrating themultiplexing processing by the prior art software. FIG. 9(a) is adiagram showing masking processing for data of processing unit, whichdata includes a code in a certain order. FIG. 9(b) is a diagram showingshifting processing for data of processing unit, which data includes acode in a next order. FIG. 9(c) is a diagram showing multiplexingprocessing for the code in the next order into the code in the certainorder.

In FIG. 9(a), numeral 901 denotes an i-th word data including a code(i)having a code length (bit length) of m_(i) bits. LSB designates a LeastSignificant Bit and MSB designates a Most Significant Bit, respectively.When a variable-length code is to be subjected to multiplexing, theprocessing is performed using data of a prescribed bit length, includingthe variable-length code. This i-th word data represents data ofprocessing unit which is used in that way. In addition, the i-th worddata 901 has the code(i) at the end on the MSB side to process the i-thword data from the MSB side.

To perform the multiplexing processing, initially, a masking data 902which has the same bit length as that of the i-th word data 901 and has“1” values in bits of a part corresponding to the code(i) and “0” valuesin bits of the other part, is generated.

Then, an OR operation of the generated masking data 902 and the i-thword data 901 is performed, and thereby-the masking processing to thei-th word data 901 for making values of bits except the code(i) “0” isperformed (903).

Then, as shown in FIG. 9(b), an i+1-th word data 904, which is aprocessing unit data in the order subsequent to the i-th word data 901and includes a code(i+1) having a m_(i+1)-bit code length, is logicallyshifted rightward (in a direction from MSB to LSB) by m_(i) bits whichcorrespond to the bit length of the code(i), thereby moving thecode(i+l) into a multiplexing position. Consequently, the i+1-th worddata 904 becomes data having “0” values in bits from the end on the MSBside to an mi-th bit and having the code(i+1) in bits subsequent to them_(i)-th bit (905).

Then, as shown in FIG. 9(c), an OR operation of the i-th word data 903which is subjected to the masking processing and the i+1-th word data905 which is subjected to the rightward shifting processing isperformed, thereby obtaining data 906 comprising the code(i) beingmultiplexed with the code(i+1) which is the code in the next order.

By performing the above-described processings successively, a bitstreamis generated by successively multiplexing codes which are successivelyinput.

FIGS. 10(a) to 10(c) are diagrams schematically illustrating the priorart demultiplexing processing by software. FIG. 10(a) is a diagram whichshows processing of extracting a code in a certain order from aprocessing unit data. FIG. 10(b) is a diagram which shows shiftingprocessing for a code of a next processing unit data. FIG. 10(c) is adiagram which shows data supplementation for the processing unit dataafter the code is extracted, from the next processing unit data.

In FIG. 10(a), numeral 911 denotes a j-th word data comprising a code(i)having a m_(i)-bit code length, a code(i+1) having a m_(i+1)-bit codelength, and a code(i+2)′ having a m_(i+2)′-bit code length. When thedemultiplexing processing is to be performed for a multiplexed code, aninput bitstream is temporarily received by an input register, and thenprocessed in a unit of the received bitstream, i.e., in a unit of thebit number of the input register. This j-th word data 911 representssuch a processing unit data of a bitstream. In the j-th word data 911,it is assumed that decoding processing is finished for the code(i), andthat the code(i+1) is to be decoded next.

To perform this demultiplexing processing, initially, this j-th worddata 911 is logically shifted leftward (in a direction from LSB to MSB)by mi bits which correspond to the bit length of the code(i), therebyextracting the code(i). Consequently, the j-th word data has thecode(i+1) and the code(i+2)′ in this order in a part of bits from theend on the MSB side to the m_(i+1)+m_(i+2′)-th bit, and has values of“0” in bits of the other part (912).

Then, as shown in FIG. 10(b), a j+1-th word data, which is the nextprocessing unit data and comprises a code(i+2)″ having a m_(i+2)″-bitcode length and a code(i+3) having a m_(i+3)-bit code length, islogically shifted rightward by m_(i+1)+m_(i+2′) bits. Thereby, thej+1-th word data becomes data having “0” values in bits from the end onthe MSB side to the m_(i+1)+m_(i+2′)-th bit, and having the code(i+2)″and a part of the code(i+3) in bits of the other part (914).

Then, as shown in FIG. 10(c), an OR operation of the j-th word data 912which is subjected to the leftward shifting processing and the j+1-thword data 914 which is subjected to the rightward shifting processing,is performed, thereby obtaining data 914 comprising a part of empty bitsgenerated by extracting the code(i) from the j-th word data 911 beingsupplemented with a part of the j+1-th word data 915.

By performing above-described processings successively, codes aresuccessively subjected to demultiplexing from the bitstreams which aresuccessively input.

In the above description, descriptions of a process for generating amasking data and a shift value setting and the like, are omitted.

However, the above-described prior art image processing system hasfollowing drawbacks.

The image processing system using MPEG2 image coding method generallyrequires real time processing, deals large quantity of image data, andfurther has a large market scale. Therefore, a special use arithmeticunit (hardware) enabling high-speed arithmetic processing is used forthe multiplexing processing for codes and the demultipliexing processingfor codes.

On the other hand, the image processing systems using the image codingmethods such as MPEG1, MPEG4, H.261, and H.263 do not have so largemarket scale. Therefore, when a special use arithmetic unit is used forthe multiplexing processing for codes and the demultiplexing processingfor codes, there may be an increase in constraints on cost oravailability for constituting the image processing system. On the otherhand, when software is employed, plural steps are required forprocessing data as described with reference to FIGS. 9(a), 9(b), 10(a),and 10(b), whereby there arises an increase in the processing time anddifficulty in performing the real time processing.

The present invention is made to solve the problems, and it is an objetof the present invention to provide an arithmetic unit able to performthe multiplexing processing for codes and the demultiplexing processingfor codes at high speeds and which thereby has versatility.

DISCLOSURE OF THE INVENTION

An arithmetic unit according to the present invention comprises an inputregister for storing a digital data which is input from outside, as aP-bit digital data, by replacing a former data with a later data, andoutputting the stored P-bit digital data, an output register forreceiving a digital data, storing the input digital data as a Q-bitdigital data, by replacing a former data with a later data, andoutputting the stored Q-bit digital data, and output bit selecting meansfor receiving the P-bit digital data which is output from the inputregister as a first input data and the Q-bit digital data which isoutput from the output register as a second input data, selecting bits,values of which bits are to be output, among bits of the first inputdata and bits of the second input data, in accordance with a controldata which is input from outside, and outputting a Q-bit digital datacomprising the values of the selected bits, to the output register.According to this structure, the digital data stored in the outputregister and the digital data stored in the input register are combinedby bit units, in accordance with the control data, and the digital datagenerated by that combination is output to the output register.Therefore, by controlling the output bit selecting means such that thedigital data generated by that combination has values of prescribed bitsof the digital data stored in the output register in prescribed bits andvalues of prescribed bits of the digital data stored in the inputregister in the other bits, a part comprising prescribed bits of thedigital data stored in the input register can be subjected tomultiplexing into a part comprising prescribed bits of the digital datastored in the output register, or a part where bits except prescribedbits of the digital data stored in the output register are extracted canbe supplemented with a part comprising prescribed bits of the digitaldata stored in the input register, besides this operation can beperformed in one cycle. Consequently, when the arithmetic unit isemployed in a coding device or a decoding device in an image processingsystem, the multiplexing processing or the demultiplexing processing forcodes can be performed at high speeds. In addition, by not utilizing thesecond input data, this arithmetic unit can be employed as a prior artshifter, thereby realizing the versatility.

In addition, according to the present invention, in the improvedarithmetic unit, the output bit selecting means uses an integer “m” asthe control data, and when the control data is input, the output bitselecting means outputs a digital data comprising bits from an end to am-th bit, which have values of bits in the same positions of the secondinput data, respectively, and bits of a m+1-th bit and following, whichhave values of bits of the first input data being arranged from an endwhich is in the same position as the Most Significant Bit side or theLeast Significant Bit side, respectively in order, as the Q-bit digitaldata. According to this structure, when the integer “m” is input as thecontrol data, the Q-bit digital data stored in the output register isreplaced by keeping the bits from an end to the m-th bit and shifting apart starting from the end on the same side of the digital data storedin the input register by m bits to move the part into the other bits.Consequently, when the arithmetic unit is employed in a coding device inan image processing system, the multiplexing processing for codes can beperformed at high speeds.

Further, according to the present invention, in the further improvedarithmetic unit, the output bit selecting means outputs digital datacomprising bits from the end on the Most Significant Bit side to them-thbit, which have values of bits in the same positions of the second inputdata, respectively, and bits of the m+1-th bit and following, which havevalues of bits of the first input data being arranged from the end onthe Most Significant Bit side, respectively in order, as the Q-bitdigital data. Therefore, the multiplexing processing for codes from theend on the Most Significant. Bit side can be performed at high speeds.

Further, according to the present invention, in the further improvedarithmetic unit, the output bit selecting means outputs digital datacomprising bits from the end on the Least Significant Bit side to them-th bit, which have values of bits in the same positions of the secondinput data, respectively, and bits of the m+1-th bit and following,which have values of bits of the first input data being arranged fromthe end on the Least Significant Bit side, respectively in order, as theQ-bit digital data. Therefore, the multiplexing processing for codesfrom the end on the Least Significant Bit side can be performed at highspeeds.

Further, according to the present invention, in the further improvedarithmetic unit, the output bit selecting means uses as the controldata, an operation mode, a shift direction, and a shift amount, inaddition to the integer “m” and when the control data having theoperation mode which indicates a mode of performing a first operationand the integer “m” is input, the output bit selecting means performsthe above operation, and when the control data having the operation modewhich indicates a mode of performing a second operation, the shiftdirection, and the shift amount is input, the output bit selecting meansoutputs a digital data which is obtained by shifting values of bits ofthe first input data in the shift direction and by the shift amount, asthe Q-bit digital data. Therefore, by only inputting a prescribedcontrol data, the arithmetic unit can also be employed as a shifter asin the prior art. As a result, the arithmetic unit enabling thehigh-speed multiplexing processing can be made to have the versatilityeasily and the shifting operation which is required in the multiplexingprocessing can be performed.

Further, according to the present invention, in the improved arithmeticunit, the output bit selecting means uses an integer “m” as the controldata, and when the control data is input, the output bit selecting meansoutputs a digital data comprising bits from an end to a Q-m-th bit,which have values of bits of the second input data being arrangedstarting from a m+1-th bit from an end which is in the same position asthe Most Significant Bit side or the Least Significant Bit side,respectively in order, and bits of a Q-m+1-th bit and following, whichhave values of bits of the first input data being arranged from an endwhich is in the same position as the Most Significant Bit side or theLeast Significant Bit side, respectively in order, as the Q-bitdigital-data. According to this structure, when the integer “m” is inputas the control data, the Q-bit digital data stored in the outputregister is replaced by extracting bits from an end to the m-th bit,shifting the other bits toward the end by the extracted bits, andshifting a part from the end on the same side to the m-th bit of thedigital data stored in the input register by Q-m bits to move the partinto bits emptied by the shifting. Consequently, when the arithmeticunit is employed in a decoding device in an image processing system, thedemultiplexing processing for codes can be performed at high speeds.

Furthermore, according to the present invention, in the further improvedarithmetic unit, the output bit selecting means outputs a digital datacomprising bits from the end on the Most Significant Bit side to theQ-m-th bit, which have values of bits of the second input data beingarranged starting from the m+1-th bit from the Most Significant Bitside, respectively in order, and bits of the Q-m+1-th bit and following,which have values of bits of the first input data being arranged fromthe end on the Most Significant Bit side, respectively in order, as theQ-bit digital data. Therefore, the demultiplexing processing for codesfrom the end on the Most Significant Bit side can be performed at highspeeds.

Furthermore, according to the present invention, in the further improvedarithmetic unit, the output bit selecting means outputs a digital datacomprising bits from the end on the Least Significant Bit side to theQ-m-th bit, which have values of bits of the second input data beingarranged starting from the m+1-th bit from the end on the LeastSignificant Bit side, respectively in order, and bits of the Q-m+1-thbit and following, which have values of bits of the first input databeing arranged from the end on the Least Significant Bit side,respectively in order, as the Q-bit digital data. Therefore, thedemultiplexing processing for codes from the end on the LeastSignificant Bit side can be performed at high speeds.

Furthermore, according to the present invention, in the further improvedarithmetic unit, the output bit selecting means uses as the controldata, an operation mode, a shift direction, and a shift amount, inaddition to the integer “m”, and when the control data having theoperation mode which indicates a mode of performing a first operationand the integer “m” is input, the output bit selecting means performsthe above operation, and when the control data having the operation modewhich indicates a mode of performing a second operation, the shiftdirection, and the shift amount is input, the output bit selecting meansoutputs a digital data which is obtained by shifting values of bits ofthe first input data in the shift direction and by the shift amount, asthe Q-bit digital data. Consequently, by only inputting a prescribedcontrol data, the arithmetic unit can also be employed as a shifter asin the prior art. As a result, the arithmetic unit enabling thehigh-speed demultiplexing processing can be made to have the versatilityeasily.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1(a) is a block diagram illustrating a structure and an operationof an arithmetic unit according to a first embodiment of the presentinvention and showing a state before arithmetic is started.

FIG. 1(b) is a block diagram illustrating the structure and theoperation of the arithmetic unit according to the first embodiment ofthe present invention and showing a state after the arithmetic isfinished.

FIG. 2 is a circuit diagram illustrating a detailed structure of anoutput bit selecting means in the arithmetic unit of FIG. 1(a).

FIG. 3 is a block diagram illustrating a structure and an operation ofan arithmetic unit according to a second embodiment of the presentinvention and showing a state after arithmetic is finished.

FIG. 4 is a circuit diagram illustrating a detailed structure of anoutput bit selecting means in the arithmetic unit of FIG. 3.

FIG. 5(a) is a block diagram illustrating a structure and an operationof an arithmetic unit according to a third embodiment of the presentinvention and showing a state before arithmetic is started.

FIG. 5(b) is a block diagram illustrating the structure and theoperation of the arithmetic unit according to the third embodiment ofthe present invention and showing a state after the arithmetic isfinished.

FIG. 6 is a circuit diagram illustrating a detailed structure of anoutput bit selecting means in the arithmetic unit of FIG. 5(a).

FIG. 7 is a block diagram illustrating a structure and an operation ofan arithmetic unit according to a fourth embodiment of the presentinvention and showing a state after arithmetic is finished.

FIG. 8 is a circuit diagram illustrating a detailed structure of anoutput bit selecting means in the arithmetic unit of FIG. 7.

FIG. 9(a) is a diagram schematically illustrating multiplexingprocessing by software in a prior art image processing system andshowing masking processing for a processing unit data including a codein a certain order.

FIG. 9(b) is a diagram schematically illustrating the multiplexingprocessing by software in the prior art image processing system andshowing shifting processing for a processing unit data including a codein the next order.

FIG. 9(c) is a diagram schematically illustrating the multiplexingprocessing by software in the prior art image processing system andshowing multiplexing processing for the code in the next order into thecode in the certain order.

FIG. 10(a) is a diagram schematically illustrating demultiplexingprocessing by software in the prior art image processing system andshowing processing of extracting a code in a certain order from aprocessing unit data.

FIG. 10(b) is a diagram schematically illustrating the demultiplexingprocessing by software in the prior art image processing system andshowing shifting processing for a code of a next processing unit data.

FIG. 10(c) is a diagram schematically illustrating the demultiplexingprocessing by software in the prior art image processing system andshowing data supplementation for the processing unit data after the codeis extracted, with data from the next processing unit data.

FIG. 11 is a circuit diagram illustrating a detailed structure of afirst or second bit selecting circuit in the output bit selecting meansof FIG. 2.

FIG. 12 is a circuit diagram illustrating a shifting operation by theoutput bit selecting means of FIG. 2.

FIG. 13 is a circuit diagram illustrating a shifting operation by thearithmetic unit of FIG. 1(a).

FIG. 14 is a block diagram illustrating a structure of a prior art imageprocessing system.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, in order to describe the present invention in more detail,embodiments of an arithmetic unit according to the present inventionwill be described with reference to the attached drawings.

EMBODIMENT 1

The first embodiment of the present invention shows an arithmetic unitemployed in a bitstream transmitting circuit in a coding unit.

FIGS. 1(a) and 1(b) are block diagrams illustrating a structure and anoperation of the arithmetic unit according to the first embodiment. FIG.1(a) is a diagram showing a state before arithmetic is started and FIG.1(b) is a diagram showing a state after the arithmetic is finished.

In these figures, the arithmetic unit comprises an 8-bit input register101 for receiving data 110 including a code, an 8-bit output register107 for outputting a multiplexed data to a memory (not shown) in alatter stage, and an output bit selecting means 105 for receiving an8-bit digital data 102 which is output from the input register 101 as afirst input data and an 8-bit digital data 103 which is output from theoutput register 107 as a second input data, selecting bits whose valuesare to be output, among bits of the first input data 102 and bits of thesecond input data 103, in accordance with a control data 104, andoutputting an 8-bit digital data 106 comprising the values of theselected bits to the output register 107 as an output data.

As described in the prior art (see FIG. 9(a)), data 110 from aprocessing unit having a prescribed bit length (8 bits in the firstembodiment), which includes a code on the MSB side, is input to theinput register 101 through other circuits (not shown) of the bitstreamtransmitting circuit. IN0 to IN7 and OUT0 to OUT7 denote values ofrespective bits from LSB to MSB, which are stored in the input register101 and the output register 107, respectively, at a starting time of acycle. In addition, IN′0 to IN′7 denote values of respective bits fromLSB to MSB, which are stored in the input register 101 at a startingtime of a next cycle.

Data including an operation mode and a residual code length, or anoperation mode, a shift amount, and a shift direction is input as thecontrol data 104 to the output bit selecting means 105 from a maincontrol circuit (not shown) of the bitstream transmitting circuit.

Next, a structure of the output bit selecting means 105 will bedescribed in detail. FIG. 2 is a circuit diagram illustrating thestructure of the output bit selecting means 105.

In the figure, the output bit selecting means 105 comprises a first bitselecting circuit 201, a second bit selecting circuit 202, an input dataselecting circuit 203, and a selector control circuit 204.

The first bit selecting circuit 201 and the second bit selecting circuit202 have 8 input terminals 201 a and 202 a and 8 output terminals 201 band 202 b, respectively. Each of the 8 output terminals 201 b in thefirst bit selecting circuit 201 can be connected to one of the 8 inputterminals 201 a, in accordance with a first selector control signal 311.Similarly, each of the 8 output terminals 202 b of the second bitselecting circuit 202 can be connected to one of the 8 input terminals202 a, in accordance with a second selector control signal 312. Here,the numbers of 0 to 7 assigned to respective terminals of the inputterminals 201 a and 202 a and the output terminals 201 b and 202 b inthe first and second bit selecting circuits 201 and 202, denotepositions of the bits of the 8-bit digital data which are input to therespective terminals or output from the respective terminals. Each ofthe input terminals 201 a in the first bit selecting circuit 201 isconnected to an output terminal (not shown) of a bit in a correspondingposition of the input register. Each of the input terminals 202 a in thesecond bit selecting circuit 202 is connected to an output terminal (notshown) of a bit in a corresponding position of the output register.

The input data selecting circuit 203 selects either of the outputterminals of bits in corresponding positions of the output terminals 201b in the first bit selecting circuit 201 and the output terminals 202 bin the second bit selecting circuit 202, for each of the outputterminals of the bits in respective positions, in accordance with athird selector control signal 313, and connects the selected outputterminal to an input terminal (not shown) of a bit in a correspondingposition in the output register.

To simplify this figure, only the connections of the output terminals201 b and 202 b to the input terminals 201 a and 202 a in the first bitselecting circuit 201 and the second bit selecting circuit 202, whoseoutputs are selected by the input data selecting circuit 203 as outputsto the input register, are shown by full lines. Since the connections ofthe output terminals 201 b and 202 b to the input terminals 201 a and202 a except above-described terminals are not selected by the inputdata selecting circuit 203 as outputs, the-connections can be decidedarbitrarily.

The selector control circuit 204 receives the control data 104 as aninput. When the control data 104 is input, the selector control circuit204 generates the first to third selector control signals 311 to 313which make the output bit selecting means 105 perform an operationindicated by the control data 104. The selector control circuit 204 thenoutputs the generated selector control signals 311 to 313 to the firstbit selecting circuit 201, the second bit selecting circuit 202, and theinput data selecting circuit 203, respectively. That is, the selectorcontrol circuit 204 outputs the selector control signals 311 to 313,which control the connections of the output terminals to the inputterminals in the first bit selecting circuit 201 and the second bitselecting circuit 202, and the selection of input sources for respectivebits by the input data selecting circuit 203, so as to make the firstbit selecting circuit 201, the second bit selecting circuit 202, and theinput data selecting circuit 203 as a whole, output an output datarequired by the control data 104. Therefore, the arithmetic unitaccording to the first embodiment can select arbitrary values amongvalues of the respective bits of the first input data and values of therespective bits of the second input data and combine the values, andoutput the combined values as output data, by inputting appropriatecontrol data to the selector control circuit 204 in the output bitselecting means 105.

In the first embodiment, when a multiplexing operation (a firstoperation) is performed, data including an operation mode and a residualcode length is input, and when a shifting operation (a second operation)is performed, data including an operation mode, a shift amount, and ashift direction is input, to the output bit selecting means 105 as thecontrol data 104. In the output bit selecting means 105, the selectorcontrol circuit 204 outputs the selector control signals 311 to 313which enable the first bit selecting circuit 201, the second bitselecting circuit 202, and the input data selecting circuit 203 toperform the operations indicated by the operation mode, the residualcode length, the shift amount, and the shift direction of the controldata 104.

The figure shows a case where the control data 104 including theoperation mode and the residual code length is input to the output bitselecting means 105. In this case, the data having data indicating“multiplexing” as the operation mode and “m bits” as the residual codelength is input as the control data 104. When the above-describedcontrol data 104 is input and assuming that m=3, in the first bitselecting circuit 201 in the output bit selecting means 105, the outputterminals of bits from the 4(=m+1)th to the 8th bits from the end on theMSB side (the output terminals of 4−0) are connected to the inputterminals of bits from the end on the MSB side to the 5th bit (the inputterminals of 7−3), and outputs of these output terminals are selected bythe input data selecting circuit 203 as outputs to the input terminals(not shown) of bits from the 4(=m+1)th to the 8th bits from the end onthe MSB side in the input register. Further, in the second bit selectingcircuit 202, the output terminals of bits from the end on the MSB sideto the 3(=m)th bit (the output terminals of 7−5) are connected to theinput terminals of bits from the end on the MSB side to the 3(=m)th bit(the input terminals of 7−5), and outputs of these output terminals areselected by the input data selecting circuit 203 as outputs to the inputterminals (not shown) of bits from the end on the MSB side to the3(=m)th bit in the input register.

FIG. 11 is a circuit diagram illustrating a structure of the first bitselecting circuit and a second bit selecting circuit in the output bitselecting means.

In the figure, since the first bit selecting circuit 201 and the secondbit selecting circuit 202 have the same structures, these are shown by acommon figure. In addition, in the description for the figure, the firstbit selecting circuit and the second bit selecting circuit are simplyreferred to as bit selecting circuits 201 and 202.

The bit selecting circuits 201 and 202 have 1st to 8th selectors 301 to308, respectively. Each of the 1st to the 8th selectors 301 to 308 hasnine input terminals and one output terminal, and the nine inputterminals of each of the selectors 301 to 308 are connected to the inputterminals 201 a and 202 a of the bit selecting circuits 201 and 202 anda “0” value input line 314, respectively. The output terminals of the1st to the 8th selectors 301 to 308 are connected to 0 to 7 of theoutput terminals 201 b and 202 b in the bit selecting circuits 201 and202, respectively. In addition, the selector control signals 311 and 312are input to the 1st to the 8th selectors 301 to 308, and in accordancewith the selector control signals 311 and 312, each of the selectors 301to 308 connects the output terminal to one of the nine input terminals.Therefore, the bit selecting circuit 201 and 202 can connect one of theinput terminals 201 a and 202 a and the “0” value input line 314 to oneof the output terminals 201 b and 202 b by receiving the appropriatecontrol signals 311 and 312, and thus arbitrarily select and combinevalues of the respective bits of the 8-bit digital data (here, the firstinput data or the second input data) which are input to the inputterminals 201 a and 202 a or “0” values, and output the combined valuesfrom the output terminals 201 b and 202 b as a 8-bit digital data. Inthe first embodiment, this combination is performed so as to enable themultiplexing processing or shifting processing, and the selector controlsignals 311 and 312 enabling such a combination are input to the bitselecting circuits 201 and 202. Here, the “0” value input line 314inputs a “0” value to an empty bit generated by the shifting when thearithmetic unit is made to operate as a shifter as in the prior art.

The input data selecting circuit 203 of FIG. 2 also has a structuresimilar to that of the bit selecting circuits 201 and 202 shown in FIG.11. That is, the input data selecting circuit 203 has eight selectorscorresponding to respective bits of an input data and an output data,and each of the eight selectors has two input terminals which areconnected to an output terminal of the first bit selecting circuit 201and an output terminal of the second bit selecting circuit 202, and oneoutput terminal which is connected to the input terminal of the outputregister. The eight selectors select inputs from the first bit selectingcircuit 201 or inputs from the second bit selecting circuit 202,respectively, in accordance with the third selector control signal 313,and output the selected inputs to the input register.

FIGS. 12 and 13 are circuit diagrams illustrating a shifting operationby the arithmetic unit. FIG. 12 is a diagram showing a state while theshifting operation is being performed. FIG. 13 is a diagram showing astate after the shifting operation is performed.

In these figures, in the output bit selecting means 105, when thecontrol data 104 indicating a shifting mode as the operation mode isinput, the selector control circuit 204 outputs, to the first bitselecting circuit 201, the first selector control signal 311 which makesthe first bit selecting circuit 201 shift the bits of the first inputdata in a direction and by an amount indicated by the control data 104and output the shifted data, as well as the selector control circuits204 outputs, to the input data selecting circuit 203, the third selectorcontrol signal 313 which makes the input data selecting circuit 203select only inputs from the first bit selecting circuit 201 for all bitsof an output data and output the same. In accordance with this firstselector control signal 311, the first bit selecting circuit 201 shiftsthe first input data in the direction and by the amount indicated by thecontrol data 104, and outputs the shifted data. In accordance with thethird selector control signal 313, the input data selecting circuit 203selects only inputs from the first bit selecting circuit 201, andoutputs the same to the input register. The figure shows a case wherethe input data is shifted leftward by 2 bits, and “0” values are inputto empty bits generated by the shifting. In addition, when the data isshifted rightward, a “0” value or a value of MSB is input to an emptybit generated by the shifting.

Next, an operation of the multiplexing processing by the arithmetic unitconstructed as described above will be described with reference to FIGS.1(a), 1(b), 2, 11, 12, and 13.

In these figures, OUT0 to OUT7, IN0 to IN7, IN′0 to IN′7, and IN″0 toIN″7 denote an i-th word data, an i+1-th word data, an i+2-th word data,and an i+3-th word data, which are described in the prior art,respectively. Further, OUT0 to OUT7, IN0 to IN7, and IN′0 to IN′7include codes having code lengths of 3 bits, 3 bits, and 4 bits,respectively.

Further, it is assumed that, in a timing of starting a cycle, the dataof OUT0 to OUT7 is stored in the output register 107 and the data of IN0to IN7 is stored in the input register 101, respectively, and thereafterthe i+2-th word data and the i+3-th word data are successively input tothe input register 101.

In the multiplexing processing, initially, in the state where a cycle isstarted as shown in FIG. 1(a), the control data 104 having an indicationdata which indicates “multiplexing” as the operation mode and “3 bits”,corresponding to a code length of a code included in the data of OUT0 toOUT7 stored in the output register 107, as the residual code length, isinput to the output bit selecting means 105 from the main controlcircuit.

Upon receipt of this input, in the output bit selecting means 105, theselector control circuit 204 outputs the first to third control signals311 to 313 which make the first bit selecting circuit 201, the secondbit selecting circuit 202, and input data selecting circuit 203 performfollowing operations.

That is, in the first bit selecting circuit 201, the output terminals ofthe bits from the 4th to the 8th bits from the end on the MSB side areconnected to the input terminals of the bits from the end on the MSBside to the 5th bit, and outputs of these output terminals are selectedby the input data selecting circuit 203 as outputs to the inputterminals of the bits from the 4th to the 8th bits from the end on theMSB side in the input register. In the second bit selecting circuit 202,the output terminals of the bits from the end on the MSB side to the 3rdbit are connected to the input terminals of the bits from the end on theMSB side to the 3rd bit, and outputs of these output terminals areselected by the input data selecting circuit 203 as outputs to the inputterminals of the bits from the end on the MSB side to the 3rd bit of theinput register. Thus, the data stored in the output register 107 isreplaced with data having values of OUT7, OUT6, and OUT5 in this orderin the bits from the end on the MSB side to the 3rd bit, and values ofIN7, IN6, IN5, IN4, and IN3 in this order in the 4th to the 8th bits,respectively, whereby the code of the i+1-th word data is subjected tomultiplexing into the code of the i-th word data.

When a next cycle is started, as shown in FIG. 1(b), the i+2-th worddata is input to the input register 101. Then, the data stored in theinput register 101 is replaced with the data of IN′7 to IN′0, as well asthe control data 104 having an indication data indicating “multiplexing”as the operation mode and “6 bits”, corresponding to a sum of both codelengths of the code of the i-th word data and the code of the i+1-thword data which are included in the data stored in the output register107, as the residual code length, is input to the output bit selectingmeans 105 from the main control circuit.

Upon receipt of this input, the output bit selecting means 105, in thesame way as in the above description, outputs data having values ofOUT7, OUT6, and OUT5 in this order in the bits from the end on the MSBside to the 3rd bit, values of IN7, IN6, and IN5 in this order in the4th to 6th bits, and values of IN′7 and IN′6 in this order in the 7thand 8th bits, whereby the data stored in the output register 107 isreplaced with this data. Thus, the code of the i+1-th word data and apart (half) of the code of the i+2-th word data are subjected tomultiplexing into the code of the i-th word data.

Since the output register 107 is filled with data obtained bymultiplexing codes, this data is transferred to a memory in a nextcycle.

When a next cycle is started, as shown in FIGS. 12 and 13, the controldata 104 having an indication data indicating “shifting” as theoperation mode, “leftward” as a shift direction, and “2 bits”,corresponding to a bit length of the remaining part of the code of thei+2-th word data, as a shift amount, is input to the output bitselecting means 105 from the main control circuit.

Upon receipt of this input, in the output bit selecting means 105, theselector control circuit 204 outputs the first and the third controlsignals 311 and 313 which make the first bit selecting circuit 201 andthe input data selecting circuit 203 perform following operations.

That is, the first bit selecting circuit 201 shifts the first input dataleftward by 2 bits and outputs the shifted input data. The input dataselecting circuit 203 selects only inputs from the first bit selectingcircuit 201 and outputs the same to the input register.

Thereby, the data of IN′7 to IN′0 stored in the input register 101 isshifted leftward by 2 bits, and data having values of IN′5, IN′4, IN′3,IN′2, IN′1, IN′0, 0, and 0 in this order from the end on the MSB side isstored in the output register 107.

Then, when a next cycle is started, the i+3-th word data is input to theinput register 101 and hereafter the multiplexing processing isperformed in the same way as in the above description.

As described above, in this first embodiment, the digital data stored inthe output register 107 and the digital data stored in the inputregister 101 are combined in bit units in accordance with the controldata 104, and the digital data 106 generated by that combination isoutput to the output register 107, and besides this operation can beperformed in one cycle. Therefore, the multiplexing processing for codescan be performed at high speeds when the unit is employed in a codingdevice in an image processing system.

EMBODIMENT 2

The second embodiment of the present invention shows an arithmetic unitwhich is employed in a bitstream transmitting circuit in a codingdevice.

FIG. 3 is a block diagram illustrating a structure and an operation ofthe arithmetic unit according to the second embodiment, and showing astate after arithmetic is finished. FIG. 4 is a circuit diagramillustrating a detailed structure of an output bit selecting means inthe arithmetic unit of FIG. 3.

In these figures, the same reference numerals as those in FIGS. 1(a),1(b), and 2 denote the same or corresponding parts. In the arithmeticunit according to the second embodiment, data lo from a processing unitwhich is input to the input register 101 has a code at the end on theLSB side. Therefore, the second embodiment is different from the firstembodiment in that data stored in the output register 107 is subjectedto multiplexing from the end on the LSB side.

In the state shown in FIG. 1(a) of the first embodiment, when a controldata 104 indicating “3 bits” as the residual code length is input to theoutput bit selecting means 105 from the main control circuit, in theoutput bit selecting means 105, the selector control circuit 204 outputsthe first to the third control signals 311 to 313 which make the firstbit selecting circuit 201, the second bit selecting circuit 202, and theinput data selecting circuit 203 perform following operations.

In the first bit selecting circuit 201, the output terminals of bitsfrom the 4th to the 8th bits from the end on the LSB side are connectedto the input terminals of bits from the end on the LSB side to the 5thbit, and the outputs of these output terminals are selected by the inputdata selecting circuit 203 as outputs to the input terminals of bitsfrom the 4th to the 8th bits from the end on the LSB side in the inputregister. In the second bit selecting circuit 202, the output terminalsof bits from the end on the LSB side to the 3rd bit are connected to theinput terminals of bits from the end on the LSB side to the 3rd bit, andoutput of these output terminals are selected by the input dataselecting circuit 203 as outputs to the input terminals of bits from theend on the LSB side to the 3rd bit in the input register. Thus, the datastored in the output register 107 is replaced with data having values ofOUT0, OUT1, and OUT2 in this order in the bits from the end on the LSBside to the 3rd bit, and values of IN0, IN1, IN2, IN3, and IN4 in thisorder in the bits from the 4th to the 8th bits. In this way, the code ofthe i+1-th word data is subjected to multiplexing from the end on theLSB side into the code of the i-th word data.

Therefore, according to the second embodiment, the multiplexingprocessing for a code from the end on the LSB side can be performed athigh speeds.

EMBODIMENT 3

The third embodiment of the present invention shows an arithmetic unitwhich is employed in a bitstream receiving circuit in a decoding device.

FIGS. 5(a) and 5(b) are block diagrams illustrating a structure and anoperation of the arithmetic unit according to the third embodiment. FIG.5(a) is a diagram showing a state before arithmetic is started and FIG.5(b) is a diagram showing a state after the arithmetic is finished.

In the figures, the same reference numerals as those in FIGS. 1(a) and1(b) denote the same or corresponding parts. The arithmetic unitaccording to the third embodiment is different from that of the firstembodiment in that it is constructed to perform the demultiplexingprocessing.

That is, as described in the prior art (see FIG. 10(a)), a bitstream 110is input to the input register 101 through other circuits (not shown) ofa bitstream receiving circuit. The input register 101 receives thisbitstream 110, in a data unit having a prescribed bit length whichcorresponds to a storage capacity (8 bits in the third embodiment), soas to include codes to be subjected to demultiplexing successively fromthe MSB side. Then, the demultiplexing processing is performed in thisdata unit received by the input register 101.

In addition, the output register 107 is connected to a variable-lengthdecoding circuit and a code situated at the end on the MSB side of adigital data stored in the output register 107 is variable-lengthdecoded by the variable-length decoding circuit.

Further, to the output bit selecting means 105, data including anoperation mode and a code length, or an operation mode, a shift amount,and a shift direction is input as a control data 104 from the maincontrol circuit (not shown) in the bitstream receiving circuit.

Next, a structure of the output bit selecting means 105 is described indetail. FIG. 6 is a circuit diagram illustrating a structure of theoutput bit selecting means 105 according to the third embodiment.

In the figure, the same reference numerals as those in FIG. 2 denote thesame or corresponding parts.

When the demultiplexing operation (first operation) is performed, dataincluding an operation mode and a code length is input to the output bitselecting means 105 as a control data 104. In this case, the controldata 104 has an indication data indicating “demultiplexing” as theoperation mode, and “m bits”, corresponding to a code length of the codesituated at the end on the MSB side in the output register, as the codelength. In addition, when a shifting operation (second operation) isperformed, data including an operation mode, a shift amount, and a shiftdirection is input as the control data 104.

When a control data having an indication data indicating“demultiplexing” as the operation mode and, for example, “3 bits” as thecode length is input to the output bit selecting means 105, in theoutput bit selecting means 105, the selector control circuit 204 outputsthe selector control signals 311 to 313 which allow the first bitselecting circuit 201, the second bit selecting circuit 202, and theinput data selecting circuit 203 to perform the demultiplexingoperation.

That is, in the second bit selecting circuit 202, the output terminalsof bits from the end on the MSB side to the 5(=8−m)th bit are connectedto the input terminals of bits from the 4(=m+1)th to the 8th bits fromthe end on the MSB side, and outputs of these output terminals areselected by the input data selecting circuit 203 as outputs to the inputterminals (not shown) of bits from the end on the MSB side to the5(=8−m)th bit in the input register. In the first bit selecting circuit201, the output terminals of bits from the 6(=8−m+1)th to the 8th bitsfrom the end on the MSB side are connected to the input terminals ofbits from the end on the MSB side to the 3(=m)th bit, and outputs ofthese output terminals are selected by the input data selecting circuit203 as outputs to the input terminals (not shown) of bits from the6(=8−m+1)th to the 8th bits from the end on the MSB side in the inputregister.

Further, the operation when the control data 104 including the operationmode, the shift amount, and the shift direction is input to the outputbit selecting means 105 is completely the same as that in the firstembodiment.

Next, the description is given of an operation of the demultiplexingprocessing by the arithmetic unit constructed as described above, withreference to FIGS. 5(a), 5(b), and 6.

In these figures, OUT0 to OUT7, IN0 to IN7, and IN′0 to IN′7 (not shown)denote a j-th word data, a j+1-th word data, and a j+2-th word data,which are described in the prior art, respectively. The data of OUT0 toOUT7 has a code(i) having a code length of 3 bits, a code(i+1) having acode length of 3 bits, and a half of a code(i+2) having a code length of4 bits in this order from the end on the MSB side. The data of IN0 toIN7 has the remaining half of the code(i+2) at the end on the MSB side.

In a timing of starting a cycle, the data of OUT0 to OUT7 is stored inthe output register 107 and the data of IN0 to IN7 is stored in theinput register 101, respectively, and hereafter data from the j+2-thword data are successively input to the input register 101.

In the demultiplexing processing, initially, in the state where a cycleis started as shown in FIG. 5(a), the code(i) situated at the end on theMSB side in the data of OUT0 to OUT7 which is stored in the outputregister 107 is decoded.

Then, the control data 104 having “demultiplexing” as the operation modeand “3 bits”, corresponding to the code length of the code(i) situatedat the end on the MSB side in the data of OUT0 to OUT7 which is storedin the output register 107, as the code length, is input to the outputbit selecting means 105 from the main control circuit.

Upon receipt of this input, in the output bit selecting means 105, theselector control circuit 204 outputs the first to the third controlsignals 311 to 313 which make the first bit selecting circuit 201, thesecond bit selecting circuit 202, and the input data selecting circuit203 perform following operations.

That is, in the second bit selecting circuit 202, the output terminalsof bits from the end on the MSB side to the 5th bit are connected to theinput terminals of bits from the 4th to the 8th bits from the end on theMSB side, and outputs of these output terminals are selected by theinput data selecting circuit 203 as outputs to the input terminals ofbits from the end on the MSB side to the 5th bit in the input register.In the first bit selecting circuit 201, the output terminals of bitsfrom the 6th to the 8th bits from the end on the MSB side are connectedto the input terminals of bits from the end on the MSB side to the 3rdbit, and outputs of these output terminals are selected by the inputdata selecting circuit 203 as outputs to the input terminals of bitsfrom the 6th to the 8th bits from the end on the MSB side in the inputregister. Thus, the data stored in the output register 107 is replacedwith data having values of OUT4, OUT3, OUT2, OUT1, and OUT0 in thisorder in the bits from the end on the MSB side to the 5th bit, andvalues of IN7, IN6, and IN5 in this order in the bits from the 6th tothe 8th bits. In this way, the code(i) is subjected to demultiplexing(extracted) from the j-th word data and empty bits in the j-th word dataare supplemented with a part of the j+1-th word data (FIG. 5(b)).

Then, in a next cycle, among the data comprising OUT4, OUT3, OUT2, OUT1,OUT0, IN7, IN6, and IN5 which is stored in the output register 107, apart comprising OUT4, OUT3, and OUT2, which corresponds to the code(i+1)is decoded. Then, the control data 104 having “3 bits”, corresponding tothe code length of the code(i+1), is input as the code length and, inthe same way as in the above description, the data stored in the outputregister 107 is replaced with data having values of OUT1, OUT0, IN7,IN6, IN5, IN4, IN3, and IN2 in this order from the end on the MSB side.Thereby, the code(i+1) is subjected to demultiplexing from the j-th worddata and empty bits in the j-th word data are supplemented with a partcomprising IN7, IN6, IN5, IN4, IN3, and IN2 of the j+1-th word data.

Then, in a next cycle, among the data comprising OUT1, OUT0, IN7, IN6,IN5, IN4, IN3, and IN2 which is stored in the output register 107, apart comprising OUT1 and OUT0, which corresponds to a half of thecode(i+2), is decoded. Then, the control data 104 having “2 bits”corresponding to a half of the code length of the code(i+2) is input asthe code length and, in the same way as in the above description, thedata stored in the output register 107 is replaced with data havingvalues of IN7, IN6, IN5, IN4, IN3, IN2, IN1, and IN0 in this order fromthe end on the MSB side. Thereby, the half of the code(i+1) is subjectedto demultiplexing from the j-th word data and empty bits in the j-thword data are supplemented with the data of IN7, IN6, IN5, IN4, IN3,IN2, IN1, and IN0, which is the entire j+1-th word data.

Thereby, the j+1-th word data which is input to the input register 101is emptied (all the data has moved to the output register 107). Then,the data of IN′0 to IN′7, which is the j+2-th word data, is input to theinput register 101 in a next cycle.

Then, in a next cycle, among the data comprising IN7, IN6, IN5, IN4,IN3, IN2, IN1, and IN0 stored in the output register 107, a partcomprising IN7 and IN6, which corresponds to the remaining half of thecode(i+2), is decoded. Then, the control data 104 having a “2 bits”,corresponding to the code length of the remaining half of the code(i+2),is input as the code length and, in the same way as in the abovedescription, the data stored in the output register 107 is replaced withdata having values of IN5, IN4, IN3, IN2, IN1, IN0, IN′7, and IN′6 inthis order from the end on the MSB side. Thereby, the remaining half ofthe code(i+2) is subjected to demultiplexing from the j+1-th word dataand empty bits in the j+1-th word data are supplemented with the partcomprising IN′7 and IN′6 of the j+2-th word data.

Hereinafter, the demultiplexing processing will be performed in the sameway as in the above description.

As described above, in this third embodiment, when the control data 104having “m bits” as a code length is input, the 8-bit digital data storedin the output register 107 is replaced by bits from the end on the MSBside to the m-th bit being extracted and the other bits corresponding tothe extracted bits being shifted toward the MSB side, and a part fromthe end on the MSB side to the m-th bit of the digital data stored inthe input register 101 being shifted by 8-m bits to move the part intobits which are emptied by the shifting, and besides this operation isperformed in one cycle. Therefore, the demultiplexing processing forcodes can be performed at high speeds, when this is employed in adecoding device in an image processing system.

EMBODIMENT 4

The fourth embodiment of the present invention shows an arithmetic unitemployed in a bitstream receiving circuit in a decoding device.

FIG. 7 is a block diagram illustrating a structure and an operation ofthe arithmetic unit according to the fourth embodiment, and showing astate after arithmetic is finished. FIG. 8 is a circuit diagramillustrating a detailed structure of an output bit selecting means inthe arithmetic unit of FIG. 7.

In these figures, the same reference numerals as those in FIGS. 5(a),5(b), and 6 denote the same or corresponding parts. The arithmetic unitaccording to the fourth embodiment is different from that in the thirdembodiment in that the input register 101 receives an input bitstream,including codes to be subjected to demultiplexing successively from theLSB side, and that a code situated at the end on the LSB side of thedata stored in the output register 107 is variable-length decoded.

In a state shown in FIG. 5(a) in the third embodiment, when a controldata having an indication data indicating “3 bits” as the code length isinput to the output bit selecting means 105 from the main controlcircuit, in the output bit selecting means 105, the selector controlcircuit 204 outputs the selector control signals 311 to 313 which makethe first bit selecting circuit 201, the second bit selecting circuit202, and the input data selecting circuit 203 perform followingoperations.

That is, in the second bit selecting circuit 202, the output terminalsof bits from the end on the LSB side to the 5th bit are connected to theinput terminals of bits from the 4th to the 8th bits from the end on theLSB side, and outputs of these output terminals are selected by theinput data selecting circuit 203 as outputs to the input terminals ofbits from the end on the LSB side to the 5th bit in the input register.In the first bit selecting circuit 201, the output terminals of bitsfrom the 6th to the 8th bit from the end on the LSB side are connectedto the input terminals of bits from the end on the LSB side to the 3rdbit, and outputs of these output terminals are selected by the inputdata selecting circuit 203 as outputs to the input terminals of bitsfrom the 6th to the 8th bits from the end on the LSB side in the inputregister.

Thus, the data stored in the output register 107 is replaced with datahaving values of OUT3, OUT4, OUT5, OUT6, and OUT7 in this order in thebits from the end on the LSB side to the 5th bit, and values of IN0,IN1, and IN2 in this order in the bits from the 6th to the 8th bits. Thecode(i) is subjected to demultiplexing from the j-th word data and emptybits in the j-th word data are supplemented with a part of the j+1-thword data (FIG. 7).

Therefore, according to the fourth embodiment, the demultiplexingprocessing for codes from the end on the LSB side can be performed athigh speeds.

In the first to the fourth embodiments, the bit length of the firstinput data is the same as the bit length of the output data. However,the bit length of the first input data can be different from the bitlength of the output data.

In addition, while the arithmetic unit is used for the multiplexingprocessing in the first and the second embodiments, the purpose of thearithmetic unit is not limited to this. For example, when two kinds of8-bit length image data are to be combined and stored in a 16-bit lengthimage memory in an image processing apparatus, the arithmetic unit canbe used for processing of combining the two kinds of 8-bit length imagedata. Further, while the arithmetic unit is used for the demultiplexingprocessing in the third and the fourth embodiments, the purpose of thearithmetic unit is not limited to this. For example, when a 16-bitlength image data stored in the image memory is to be output anddemultiplexed into two kinds of 8-bit length image data in the imageprocessing apparatus, the arithmetic unit can be used for thedemultiplexing processing for the 16-bit length image data.

Further, the arithmetic units according to the first to the fourthembodiments can be employed as a prior art shifter and for example canbe employed as a shifter in the respective circuits 3 to 5 and 11 to 13in the coding device 1 and the decoding device 9 shown in FIG. 14. Inthis case, as described in the first to the fourth embodiments, thearithmetic unit can be made to operate as a shifter by inputting aprescribed control data. In this way, the arithmetic units according tothe first to the fourth embodiments can be employed as a prior artshifter, thereby realizing the versatility.

Industrial Availability

As described above, the arithmetic unit according to the presentinvention is useful as an arithmetic unit which performs multiplexingprocessing for codes and the demultiplexing processing for codes in animage processing system, and particularly suitable for use in an imageprocessing system requiring a high-speed processing.

1-9. (canceled)
 10. A processor comprising: a first register for storinga first data; and a second register for storing a second data, whereinsaid processor outputs a higher part of the first data as a lower partof an output data and outputs a lower part of a second data as a higherpart of the output data in one cycle.
 11. The processor of claim 10,wherein a shifted lower part of the second data comprises the lower partof the second data.
 12. A method of processing P-bit length data andQ-bit length data, said method comprising: storing a P-bit length dataand a Q-bit length data; and outputting a processed data having a higherpart and a lower part in one cycle, wherein the lower part of theprocessed data comprises a higher part of the P-bit length data, whereinthe higher part of the processed data comprises a lower part of theQ-bit length data, wherein the higher part of the P-bit length data is mbits in length, wherein the lower part of the Q-bit length data is nbits in length, and wherein a bit length of the P-bit length data, theQ-bit length data and the processed data are equal to m+n bits inlength.
 13. The method of claim 12, wherein a shifted lower part of theQ-bit length data comprises the lower part of the Q-bit length data. 14.A processor comprising: a first register for storing a first data; and asecond register for storing a second data, wherein the processor outputsa processed data having a higher part and a lower part, wherein thelower part of the processed data comprises a higher part of the firstdata, wherein the higher part of the processed data comprises a lowerpart of the second data.
 15. The processor of claim 14, wherein a bitlength of the first data is equal to P-bit length data, wherein a bitlength of the second data is equal to Q-bit length data, wherein thehigher part of the P-bit length data is m bits in length, wherein thelower part of the Q-bit length data is n bits in length, and wherein abit length of the P-bit length data, the Q-bit length data and theprocessed data are equal to m+n bits in length.
 16. The processor ofclaim 15, wherein m+n bits are a multiple of
 8. 17. The processor ofclaim 16, wherein a shifted lower part of the Q-bit length datacomprises the lower part of the Q-bit length data.